A network processor is one example of what is more generally referred to herein as a link layer device, where the term “link layer” generally denotes a switching function layer. Such link layer devices can be used to implement packet-based protocols, such as Internet Protocol (IP) and Asynchronous Transfer Mode (ATM), and are also commonly known as Layer-3 (L3) devices in accordance with the well-known Open System Interconnect (OSI) model.
Communication between a physical layer device and a network processor or other type of link layer device may be implemented in accordance with an interface standard, such as the SPI-3 interface standard described in Implementation Agreement OIF-SPI3-01.0, “System Packet Interface Level 3 (SPI-3): OC-48 System Interface for Physical and Link Layer Devices,” Optical Internetworking Forum, 2001, which is incorporated by reference herein.
A given physical layer device may comprise a multiple-port device which communicates over multiple channels with the link layer device. Such communication channels, also commonly known as MPHYs, may be viewed as examples of what are more generally referred to herein as physical layer device ports. A given set of MPHYs that are coupled to a link layer device may comprise multiple ports associated with a single physical layer device, multiple ports each associated with one of a plurality of different physical layer devices, or combinations of such arrangements. As is well known, a link layer device may be advantageously configured to detect backpressure (BP) for a particular MPHY via polling of the corresponding MPHY address on the physical layer device. The detected backpressure is used by the link layer device to provide flow control and other traffic management functions, thereby improving link utilization.
U.S. patent application Ser. No. 10/689,090 filed Oct. 20, 2003 and entitled “Traffic Management Using In-band Flow Control and Multiple-rate Traffic Shaping,” discloses improved techniques for communicating information between a link layer device and a physical layer device, so as to facilitate backpressure detection and related traffic management functions, particularly in high channel count (HCC) packet-based applications.
A significant problem that can arise when utilizing a conventional SPI-3 interface for communication between a physical layer device and a link layer device is that insufficient configurability of the interface address pins is provided. For example, a typical implementation of the SPI-3 interface may separate a single 32-bit bus into multiple 16-bit buses, multiple 8-bit buses, or a combination of a 16-bit bus and one or more 8-bit buses.
In such an arrangement, the conventional approach is to provide a fixed allocation of a certain number of the address bits to each of the sub-buses, in accordance with the ratio of the size of the sub-bus to the single 32-bit bus. Thus, each 8-bit sub-bus will always be allocated one-fourth of the address bits associated with the 32-bit bus, while each 16-bit sub-bus will always be allocated one-half of the address bits associated with the 32-bit bus.
The disadvantage of this fixed allocation approach, as indicated previously, is that it fails to provide sufficient flexibility in allocation of the available address bits to the various sub-buses. The approach automatically assumes that a smaller sub-bus requires fewer address pins than a larger sub-bus, and that sub-buses of the same size require the same number of address pins, when such assumptions are not necessarily true. Thus, the fixed allocation approach does not provide optimal address pin allocations in many interface applications.
Accordingly, a need exists for a more flexible approach to allocating address bits to sub-buses of an interface bus between a physical layer device and a link layer device.